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課程名稱 (中文) 計算機組織
(英文) Computer Organization
開課單位 電機工程學系
課程代碼 E2550B
授課教師 周俊賢
學分數 3.0 必/選修 選修 開課年級 大三
先修科目或先備能力:計算機概論、組合語言、邏輯設計
課程概述與目標: 本課程為讓學生深入了解計算機組織內容及軟硬體間之介面探討。學生將可從課程中學到如何利用硬體描述語言設計CPU。主要內容除觀察計算機基本架構之歷史演變之外,將包括指令集架構(Instruction Set Architecture, ISA)、算數運算及邏輯運算單元、資料路徑(datapath)及控制器,儲存系統、輸入-輸出系統、網路中斷及異常處理等之性能分析及設計。
教科書 1.David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, ARM Edition. (東華書局代理)
參考教材 1.John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach,

3.http://bwrc.eecs.berkeley.edu/CIC/
4.VHDL cookbook & Ver
課程大綱 學生學習目標 單元學習活動 學習成效評量 備註
單元主題 內容綱要
1 Computer Abstractions and Technology 1. Introduction to computer organization
2. Organization and anatomy of a computer
計算機發展沿革
Get to know what is all about computer organization and the basic components that constitute a computer
  • 講授
  • Homework of Chapter 1  
    2 Computer Abstractions and Technology 1. Performance evaluation
    2. The power wall
    3. The Sea Change
    4. IT development stages
    計算機計量設計方法的基本原則
    The basic concepts involved in designing computers.
    Fundamentals of computer design.
  • 講授
  • Homework of Chapter 1  
    3 Instructions: Language of the computer 1.Instruction set architecture
    2. Representation of Instructions
    3. Logical Operations
    4. Principles of instruction set design for RISC
    計算機指令集扮演的角色與重要性
    RISC指令集的重要特性
    The role of Instruction set in computer design.
    Operations, operands, numbers and the representation of instructions.
  • 講授
  • Homework of Chapter 2  
    4 Instructions: Language of the computer 1. MIPS instruction format
    2. Instructions for Making Decisions
    3. Procedures in Computer Hardware
    4. Addressing modes
    5. Instruction formats of ARM processors
    指令集的編碼與格式
    MIPS與ARMS範例說明
    Instruction set of MIPS
    Logical operations
    Control flow instructions for
    Procedures in Computer Hardware
  • 講授
  • Homework of Chapter 2  
    5 Arithmetic for Computers 1. Addition
    2. Subtraction
    3. Multiplication
    4. Division
    To understand the primary computation carried out in ALU(arithmetic and logic unit)
  • 講授
  • Homework of Chapter 3 Quiz 1  
    6 Arithmetic for Computers 1. IEEE 754 standard and the floating point operations in MIPS
    2. Parallelism and computer arithmetic associativity
    To understand the primary computation carried out in ALU(arithmetic and logic unit)
  • 講授
  • 平時考
  • Homework of Chapter 3 Quiz 1  
    7 Pipelining 1. Classification of pipelines
    2. Space-time analysis of a pipeline
    pipeline 平行處理之基本原理
    pipeline 處理之分類與型別
    Concept of pipelining
    Performance evaluation of a pipeline
  • 講授
  • Homework of Chapter 3 Quiz 1  
    8 Pipelining 1. Latency analysis of a pipeline
    2. Designed of nonlinear and multifunctional pipelines
    3. Optimization in designing a pipeline
    pipeline 的系統化設計
    Procedure for designing a pipeline
  • 實作
  • 講授
  • Homework of Chapter 3 Quiz 1  
    9 Pipelined arithmetic units 1. Pipelined design of floating-point adders
    2. Pipelined design of multipliers
    Pipelined operations in ALU
  • 實作
  • 講授
  • 期中考
  • Homework of Chapter 4 Midterm Examination  
    10 The Processor 1. Logic Design Conventions
    2. Building a Datapath
    3. Pipelined Datapath and Control
    4. Instruction pipelines
    The design of the Instruction pipeline in MIPS
  • 講授
  • Homework of Chapter 4 Midterm Examination  
    11 The Processor 1. Pipeline Hazards
    2. Control Hazards
    3. Exceptions
    以pipeline方式執行指令的處理器設計
    認識 instruction pipeline執行指令時可能遭遇的危障
    instruction pipeline在遭遇程式中斷時的處理方法
  • 講授
  • Homework of Chapter 4 Midterm Examination  
    12 Instruction-level Parallelism Advanced Instruction-level Parallelism Parallelism among instructions
  • 講授
  • Homework of Chapter 4 Midterm Examination  
    13 Instruction level paralleism 1. Forwarding and bypassing
    2. Branch slot scheduling
    Instruction pipeline 平行處理的硬體解決方法
    利用delay slot 在instruction pipeline 平行處理的軟體(compiler)解決方法
  • 講授
  • 平時考
  • Homework of Chapter 4  
    14 Instruction level paralleism 1. Loop unrolling and software pipelining
    2. Dynamic branch prediction
    Instruction pipeline 平行處理的軟體解決方法
    Instruction pipeline解決control hazard 的硬體解決方法
  • 講授
  • Homework of Chapter 4  
    15 Instruction level paralleism 1. Multiple-issue operation of the instruction pipeline
    2. The out of order problem of the instruction pipeline
    instruction pipeline之多重指令發出平行處理設計
    instruction pipeline平行處理多重指令時面臨之失序完成時點問題
  • 講授
  • Homework of Chapter 5  
    16 Instruction level paralleism : Dynamic scheduling 1. The Scoreboarding method for dynamic instruction scheduling
    2. Dynamic instruction scheduling with renaming
    學習指令動態排程的目的與方法
    中央處理機制的排程方法
    分散式處理機制的排程方法
  • 實作
  • 講授
  • 平時考
  • Homework of Chapter 5  
    17 Memory hierarchy design 1. Virtual memory concept
    2. Main memory and organizations for high-speed computers
    虛擬記憶體觀念
    高存取速度之主記憶體設記概念與方法
  • 講授
  • Homework of Chapter 5  
    18 Memory hierarchy design 1. Design of Cache
    2. Reducing cache miss penalty and miss rate
    快取記憶體的目的與設計概念
    快取記憶體的優化設計方法
  • 講授
  • Homework of Chapter 5  
    19 Storage and Other I/O Topics 1. Dependability, Reliability and Availability
    2. Disk Storage
    3. Flash Storage
    4. Connecting P, M and I/O
    5. I/O Performance Measures
    6. Designing I/O System
    Basic concepts of designing Storage and I/O systems
    Performance Measures of Storage and I/O Systems
  • 講授
  • 期末考
  • Homework of Chapter 6  

    教學要點概述:
    教材編選: □ 自編教材 ■ 教科書作者提供
    評量方法: 平時考:40%   期中考:30%   期末考:30%  
    教學資源: ■ 教材電子檔 □ 課程網站
    教學相關配合事項:液晶投影機, Tablet PC
    課程網站:校園網路硬碟二 分享檔名 E2550A4dav
    扣考規定:http://eboard.ttu.edu.tw/ttuwebpost/showcontent-news.php?id=504

    大學部
    核心能力 平時考 期中考 期末考
    核心能力一 運用數學、科學及電機相關工程知識的能力。 1/10 1 1 1
    核心能力二 設計與執行實驗,以及分析與解釋數據的能力。 1/10 1 1 1
    核心能力三 執行電機相關工程實務所需技術、技巧及使用工具之能力。 4/10 4 4 4
    核心能力四 設計電機相關工程系統、元件或製程之能力。 2/10 2 2 2
    核心能力六 發掘、分析及處理問題的能力。 2/10 2 2 2