教學大綱表 (111學年度 第2學期)
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課程名稱
Course Title		 (中文) 計算機組織
(英文) Computer Organization 		開課單位
Departments		 電機工程學系
課程代碼
Course No.		 E2550
授課教師
Instructor		 周俊賢
學分數
Credit		 3.0 必/選修
core required/optional		 選修 開課年級
Level		 大三
先修科目或先備能力(Course Pre-requisites)：計算機概論、組合語言、邏輯設計
課程概述與目標(Course Overview and Goals)： 本課程為讓學生深入了解計算機組織內容及軟硬體間之介面探討。學生將可從課程中學到如何利用硬體描述語言設計CPU。主要內容除觀察計算機基本架構之歷史演變之外，將包括指令集架構(Instruction Set Architecture, ISA)、算數運算及邏輯運算單元、資料路徑(datapath)及控制器，儲存系統、輸入－輸出系統、網路中斷及異常處理等之性能分析及設計。
教科書(Textbook) 1.David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, ARM Edition. (東華書局代理)
參考教材(Reference) 1.John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach,

3.http://bwrc.eecs.berkeley.edu/CIC/
4.VHDL cookbook & Ver
課程大綱 Syllabus 學生學習目標
Learning Objectives		 單元學習活動
Learning Activities		 學習成效評量
Evaluation		 備註
Notes
序
No.		 單元主題
Unit topic		 內容綱要
Content summary
1 Computer Abstractions and Technology 1. Introduction to computer organization
2. Organization and anatomy of a computer 		計算機發展沿革
Get to know what is all about computer organization and the basic components that constitute a computer		 Homework of Chapter 1  
2 Computer Abstractions and Technology 1. Performance evaluation
2. The power wall
3. The Sea Change
4. IT development stages 		計算機計量設計方法的基本原則
The basic concepts involved in designing computers.
Fundamentals of computer design.		 Homework of Chapter 1  
3 Instructions: Language of the computer 1.Instruction set architecture
2. Representation of Instructions
3. Logical Operations
4. Principles of instruction set design for RISC 		計算機指令集扮演的角色與重要性
RISC指令集的重要特性
The role of Instruction set in computer design.
Operations, operands, numbers and the representation of instructions.		 Homework of Chapter 2  
4 Instructions: Language of the computer 1. MIPS instruction format
2. Instructions for Making Decisions
3. Procedures in Computer Hardware
4. Addressing modes
5. Instruction formats of ARM processors 		指令集的編碼與格式
MIPS與ARMS範例說明
Instruction set of MIPS
Logical operations
Control flow instructions for
Procedures in Computer Hardware		 Homework of Chapter 2  
5 Arithmetic for Computers 1. Addition
2. Subtraction
3. Multiplication
4. Division 		To understand the primary computation carried out in ALU(arithmetic and logic unit) Homework of Chapter 3 Quiz 1  
6 Arithmetic for Computers 1. IEEE 754 standard and the floating point operations in MIPS
2. Parallelism and computer arithmetic associativity 		To understand the primary computation carried out in ALU(arithmetic and logic unit) Homework of Chapter 3 Quiz 1  
7 Pipelining 1. Classification of pipelines
2. Space-time analysis of a pipeline 		pipeline 平行處理之基本原理
pipeline 處理之分類與型別
Concept of pipelining
Performance evaluation of a pipeline		 Homework of Chapter 3 Quiz 1  
8 Pipelining 1. Latency analysis of a pipeline
2. Designed of nonlinear and multifunctional pipelines
3. Optimization in designing a pipeline 		pipeline 的系統化設計
Procedure for designing a pipeline		 Homework of Chapter 3 Quiz 1  
9 Pipelined arithmetic units 1. Pipelined design of floating-point adders
2. Pipelined design of multipliers 		Pipelined operations in ALU Homework of Chapter 4 Midterm Examination  
10 The Processor 1. Logic Design Conventions
2. Building a Datapath
3. Pipelined Datapath and Control
4. Instruction pipelines 		The design of the Instruction pipeline in MIPS Homework of Chapter 4 Midterm Examination  
11 The Processor 1. Pipeline Hazards
2. Control Hazards
3. Exceptions 		以pipeline方式執行指令的處理器設計
認識 instruction pipeline執行指令時可能遭遇的危障
instruction pipeline在遭遇程式中斷時的處理方法		 Homework of Chapter 4 Midterm Examination  
12 Instruction-level Parallelism Advanced Instruction-level Parallelism Parallelism among instructions Homework of Chapter 4 Midterm Examination  
13 Instruction level paralleism 1. Forwarding and bypassing
2. Branch slot scheduling 		Instruction pipeline 平行處理的硬體解決方法
利用delay slot 在instruction pipeline 平行處理的軟體(compiler)解決方法		 Homework of Chapter 4  
14 Instruction level paralleism 1. Loop unrolling and software pipelining
2. Dynamic branch prediction 		Instruction pipeline 平行處理的軟體解決方法
Instruction pipeline解決control hazard 的硬體解決方法		 Homework of Chapter 4  
15 Instruction level paralleism 1. Multiple-issue operation of the instruction pipeline
2. The out of order problem of the instruction pipeline 		instruction pipeline之多重指令發出平行處理設計
instruction pipeline平行處理多重指令時面臨之失序完成時點問題		 Homework of Chapter 5  
16 Instruction level paralleism : Dynamic scheduling 1. The Scoreboarding method for dynamic instruction scheduling
2. Dynamic instruction scheduling with renaming 		學習指令動態排程的目的與方法
中央處理機制的排程方法
分散式處理機制的排程方法		 Homework of Chapter 5  
17 Memory hierarchy design 1. Virtual memory concept
2. Main memory and organizations for high-speed computers 		虛擬記憶體觀念
高存取速度之主記憶體設記概念與方法		 Homework of Chapter 5  
18 Memory hierarchy design 1. Design of Cache
2. Reducing cache miss penalty and miss rate 		快取記憶體的目的與設計概念
快取記憶體的優化設計方法		 Homework of Chapter 5  
19 Storage and Other I/O Topics 1. Dependability, Reliability and Availability
2. Disk Storage
3. Flash Storage
4. Connecting P, M and I/O
5. I/O Performance Measures
6. Designing I/O System 		Basic concepts of designing Storage and I/O systems
Performance Measures of Storage and I/O Systems		 Homework of Chapter 6  


教學要點概述：
1.自編教材 Handout by Instructor：
□ 1-1.簡報 Slids
□ 1-2.影音教材 Videos
□ 1-3.教具 Teaching Aids
□ 1-4.教科書 Textbook
□ 1-5.其他 Other
□ 2.自編評量工具/量表 Educational Assessment
□ 3.教科書作者提供 Textbook

成績考核 Performance Evaluation： 期末考：30%   期中考：30%   平時考：30%   作業：10%  

教學資源(Teaching Resources)：
□ 教材電子檔(Soft Copy of the Handout or the Textbook)
□ 課程網站(Website)
教學相關配合事項：液晶投影機, Tablet PC
課程網站(Website)：校園網路硬碟二 分享檔名 E2550A4dav
扣考規定：http://eboard.ttu.edu.tw/ttuwebpost/showcontent-news.php?id=504