| 課程大綱 Syllabus |
學生學習目標
Learning Objectives |
單元學習活動
Learning Activities |
學習成效評量
Evaluation |
備註
Notes |
序
No. | 單元主題
Unit topic |
內容綱要
Content summary |
| 1 | Introduction |
Course Introduction
Overview of the IC Design Flow
Lab 1: Cadence® -- Schematic Design |
Introduction
VLSI Design Flow |
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| 2 | Circuit Simulation |
Lab 2: Hspice Circuit Simulation |
Learn how to use Hspice for circuit simulation |
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| 3 | CMOS Process and Layout |
CMOS Process
CMOS Circuit Layout
Layout Design Rules
Lab 3: Cadence® -- Virttuo |
Learn how to use Cadence Virtuso for Layout |
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| 4 | CMOS Process and Layout |
CMOS Process
CMOS Circuit Layout
Layout Design Rules
Lab 3: Cadence® -- Virttuo |
Learn how to use Cadence Virtuso for Layout |
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| 5 | Layout Verification |
Design Rule Check (DRC)
Layout vs Schematic (LVS)
Prasitic Extractio (PEX)
Post-Layout Simulation
Lab 4: Calibre |
Learn how to use Calibre for layout verification |
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| 6 | Layout Project |
Design Rule Check (DRC)
Layout vs Schematic (LVS)
Prasitic Extractio (PEX)
Post-Layout Simulation |
Layout Project |
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| 7 | Layout Project |
Design Rule Check (DRC)
Layout vs Schematic (LVS)
Prasitic Extractio (PEX)
Post-Layout Simulation |
Layout Project |
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| 8 | Logic-Level Simulation – Verilog |
Introduction to Verilog
Introduction of NC-Verilog |
Learn how to model combinational circuits by using Verilog structural modeling. |
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| 9 | Logic-Level Simulation – Verilog |
Structral Modeling of MUX and adder |
Structral Modeling of MUX and adder |
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| 10 | Verilog – RTL Modeling |
Behavioral modeling
Verilog Examples |
Verilog behavioral modeling |
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| 11 | Verilog – RTL Modeling |
Verilog Examples
ALU and FIR filter behaviorial modeling |
Learn how to model circuits by using Verilog behavioral modeling. NC-Verilog will be used to verify the circuits. |
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| 12 | Verilog – Finite-State Machine |
Modeling and testig a FSM |
Learn how to use Verilog HDL to model and test a serial input bit-stream pattern detector and a one’s counter. |
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| 13 | Logic Synthesis – Synopsys |
Concept of logic synthesis
Synthesis tool -- Synopsys |
Learn the concept of logic synthesis and get familiar with the synthesis tool -- Synopsys. |
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| 14 | Logic Synthesis – Synopsys & Cell Library Design |
Synthesizing the RTL code into the gate level design using cell library |
Synthesizing the RTL code into the gate level design using cell library |
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| 15 | Logic Synthesis – Synopsys & Cell Library Design |
Synthesizing the RTL code into the gate level design using cell library |
Synthesizing the RTL code into the gate level design using cell library |
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| 16 | Cell-Based IC Physical Design and Verification |
Cell-based IC physical design concept |
Cell-based IC physical design concept |
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