課程名稱 |
(中文) 鎖相迴路 (英文) Phase Lock Loop |
開課單位 | 電機工程研究所 | ||
課程代碼 | E5240 | ||||
授課教師 | 林明郎 | ||||
學分數 | 3.0 | 必/選修 | 選修 | 開課年級 | 研究所 |
先修科目或先備能力:邏輯設計、電子學 | |||||
課程概述與目標:鎖相迴路主要是運用回受系統原理,讓參考信號及回受信號的相位一致,並運用相位鎖定的技術來設計頻率合成器,並將此技術應用於信號的調變及解調變、時脈及資料回復電路設計。為了讓資料可以正確回復,具備低抖動及低偏疑的鎖相迴路就非常重要。 | |||||
教科書 | Roland E. Best, “Phase‐Locked Loops: Design, Simulation, and applications 6th”, McGraw Hill, 2007 Behzad Razavi, “Design of Integrated Circuits for Optical Communications", McGraw Hill, 2003 |
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參考教材 | Keliu Shu, “CMOS PLL Synthesizers: Analysis and Design”, Springer, 2005 homas H. Lee, “Multi‐GHz Frequency Syhthesis & Division”, KLUWER A.P. , 2001 C‐K Ken Yang, “Phase‐Locking in High‐Performance Systems: From Devices to Architectures”, 2003 |
課程大綱 | 學生學習目標 | 單元學習活動 | 學習成效評量 | 備註 | ||
週 | 單元主題 | 內容綱要 | ||||
1 | Introduction to Phase locked loop | 1. Why use PLL 2. What is PLL 3. Basic concept of PLL |
1. Understand PLL and its application 2. Understand Basic concept of PLL |
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2 | Introduction to Phase locked loop | 1. Basic concept of PLL 2. linear model PLL |
Understand 1. Basic concept of PLL 2. linear model PLL |
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3 | Introduction of Charge-pump PLL | 1. What is CP-PLL 2. Basic component of CP-PLL 3. Features of CP-PLL 4.Basic concept of Charge-pump PLL 5.Type I,II,III of CP-PLL and its linear model |
Understand 1. What is CP-PLL 2. Basic component of CP-PLL 3. Features of CP-PLL 4.Basic concept of Charge-pump PLL 5.Type I,II,III of CP-PLL and its linear model |
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4 | Desin of CP-PLL | Design procedure of CP-PLL | understand Design procedure of CP-PLL |
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5 | Static and Dynamic circuit of D Flip-Flop | 1. DFF Implementation in SR-latch 2. DFF Implementation in TSPC 3. DFF Implementation in E-TSPC 4. Setup and Hold time investgation of DFFs |
Understand 1. DFF Implementation in SR-latch 2. DFF Implementation in TSPC 3. DFF Implementation in E-TSPC 4. Setup and Hold time investgation of DFFs |
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6 | Implementation of PLL | Implementation of Phase frequency detector | Know how to design the circuit of phase frequency detector | |||
7 | Implementation of PLL | Implementation of charge pump circuit | understand how to design the circuit of charge pump circuit |
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8 | Implementation of PLL | Implementation of loop filter | understand how to design the circuit of loop filter |
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9 | 期中考 | 期中考 | 期中考 | |||
10 | Implementation of PLL | Implementation of VCO: ring oscillator | understand how to design ring oscillator |
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11 | Implementation of PLL | Implementation of VCO: LC-tanked oscillator | Understand how to design the circuit of VCO: LC-tanked oscillator |
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12 | Implementation of PLL | Implementation of Frequency divider synchronous Counter design |
know how eo desgn : Frequency divider synchronous Counter design |
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13 | Implementation of PLL | Implementation of Frequency divider synchronous Counter design |
know how eo desgn : Frequency divider synchronous Counter design |
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14 | Nonideal effects in PLLs | Nonideal effects in PLLs: phase mismatch, current mismatch, limitation of component...etc. |
Nonideal effects in PLLs: phase mismatch, current mismatch, limitation of component...etc. |
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15 | Delay locked loops | 1. concept of Delay locked loop 2. linear model of Delay locked loop |
1. concept of Delay locked loop 2. linear model of Delay locked loop |
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16 | Fractional Frequency Synthesizer | 1. concept of Fractional Frequency Synthesizer 2. operation of Fractional Frequency Synthesizer |
1. concept of Fractional Frequency Synthesizer 2. operation of Fractional Frequency Synthesizer |
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17 | Final project representation | Final project representation | learn the skill of representation, team work |
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18 | 期末考 | 期末考 | 期末考 |
教學要點概述: |