課程大綱 Syllabus |
學生學習目標 Learning Objectives |
單元學習活動 Learning Activities |
學習成效評量 Evaluation |
備註 Notes |
序 No. | 單元主題 Unit topic |
內容綱要 Content summary |
1 | Introduction to Phase locked loop |
1. Why use PLL
2. What is PLL
3. Basic concept of PLL |
1. Understand PLL and its application
2. Understand Basic concept of PLL |
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2 | Introduction to Phase locked loop |
1. Basic concept of PLL
2. linear model PLL |
Understand
1. Basic concept of PLL
2. linear model PLL |
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3 | Introduction of Charge-pump PLL |
1. What is CP-PLL
2. Basic component of CP-PLL
3. Features of CP-PLL
4.Basic concept of Charge-pump PLL
5.Type I,II,III of CP-PLL and its linear model |
Understand
1. What is CP-PLL
2. Basic component of CP-PLL
3. Features of CP-PLL
4.Basic concept of Charge-pump PLL
5.Type I,II,III of CP-PLL and its linear model |
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4 | Desin of CP-PLL |
Design procedure of CP-PLL |
understand Design procedure of CP-PLL |
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5 | Static and Dynamic circuit of D Flip-Flop |
1. DFF Implementation in SR-latch
2. DFF Implementation in TSPC
3. DFF Implementation in E-TSPC
4. Setup and Hold time investgation of DFFs |
Understand
1. DFF Implementation in SR-latch
2. DFF Implementation in TSPC
3. DFF Implementation in E-TSPC
4. Setup and Hold time investgation of DFFs |
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6 | Implementation of PLL |
Implementation of Phase frequency detector |
Know how to design the circuit of phase frequency detector |
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7 | Implementation of PLL |
Implementation of charge pump circuit |
understand how to design the circuit of charge pump circuit |
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8 | 期中考 |
期中考 |
期中考 |
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9 | Implementation of PLL |
Implementation of VCO: ring oscillator |
understand how to design ring oscillator |
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10 | Implementation of PLL |
Implementation of VCO: LC-tanked oscillator |
Understand how to design the circuit of VCO: LC-tanked oscillator |
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11 | Implementation of PLL |
Implementation of Frequency divider
synchronous Counter design |
know how eo desgn :
Frequency divider
synchronous Counter design |
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12 | Implementation of PLL |
Implementation of Frequency divider
synchronous Counter design |
know how eo desgn :
Frequency divider
synchronous Counter design |
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13 | Nonideal effects in PLLs |
Nonideal effects in PLLs:
phase mismatch, current mismatch, limitation of component...etc. |
Nonideal effects in PLLs:
phase mismatch, current mismatch, limitation of component...etc. |
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14 | Delay locked loops |
1. concept of Delay locked loop
2. linear model of Delay locked loop |
1. concept of Delay locked loop
2. linear model of Delay locked loop |
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15 | Fractional Frequency Synthesizer |
1. concept of Fractional Frequency Synthesizer
2. operation of Fractional Frequency Synthesizer |
1. concept of Fractional Frequency Synthesizer
2. operation of Fractional Frequency Synthesizer |
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16 | 期末考 |
期末考 |
期末考 |
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