I2150 教學大綱表

教學大綱表 (112學年度第1學期)

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課程名稱 Course Title	(中文) 邏輯設計 (英文) Logic Design			開課單位 Departments	資訊工程學系
				課程代碼 Course No.	I2150
授課教師 Instructor	柯振揚
學分數 Credit	3.0	必/選修 core required/optional	必修	開課年級 Level	大二
先修科目或先備能力(Course Pre-requisites)：
課程概述與目標(Course Overview and Goals)：Introduction to basic knowledge and methodologies of logic design, and to develop a foundation that can be used as the basis for further study and research in this field.
教科書(Textbook)	M. Morris Mano and Michael D. Ciletti, Digital Design, 6th Ed., Pearson Prentice Hall, 2019.
參考教材(Reference)	C. H. Roth, Fundamentals of Logic Design, 7th Ed., Cengage Learning, 2013 S. Brown & Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, McGRAW Hill

課程大綱 Syllabus			學生學習目標 Learning Objectives	單元學習活動 Learning Activities	學習成效評量 Evaluation	備註 Notes
序 No.	單元主題 Unit topic	內容綱要 Content summary	學生學習目標 Learning Objectives	單元學習活動 Learning Activities	學習成效評量 Evaluation	備註 Notes
1	1. Digital Systems and Binary Numbers	Digital Systems Binary Numbers Number-base conversion Complements	Digital Systems Binary Numbers Number-base conversion Complements
2	1. Digital Systems and Binary Numbers	Digital Systems Binary Numbers Number-base conversion Complements	Digital Systems Binary Numbers Number-base conversion Complements
3	2. Boolean Algebra and Logic Gates	Boolean algebra Boolean functions Digital logic gates	Boolean algebra Boolean functions Digital logic gates
4	2. Boolean Algebra and Logic Gates	Boolean algebra Boolean functions Digital logic gates	Boolean algebra Boolean functions Digital logic gates
5	3. Gate-level minimization	Map method SOP simplification POS simplification Don't care conditions NAND an NOR circuits	Map method SOP simplification POS simplification Don't care conditions NAND an NOR circuits
6	3. Gate-level minimization	Map method SOP simplification POS simplification Don't care conditions NAND an NOR circuits	Map method SOP simplification POS simplification Don't care conditions NAND an NOR circuits
7	4. Commbinational logic	Binary adder-subtractor Decimal adder Binart multiplier Magnitude comparator Decoders Encoders Multiplexers	Binary adder-subtractor Decimal adder Binart multiplier Magnitude comparator Decoders Encoders Multiplexers
8	期中考週	期中考週	期中考週
9	4. Commbinational logic	Binary adder-subtractor Decimal adder Binart multiplier Magnitude comparator Decoders Encoders Multiplexers	Binary adder-subtractor Decimal adder Binart multiplier Magnitude comparator Decoders Encoders Multiplexers
10	5. Synchronous sequential logic	Sequential circuits Latches Flip-flops Analysis of clocked models sequential circuits Design a clocked models sequential circuits State reduction and assignment	Sequential circuits Latches Flip-flops Analysis of clocked models sequential circuits Design a clocked models sequential circuits State reduction and assignment
11	5. Synchronous sequential logic	Sequential circuits Latches Flip-flops Analysis of clocked models sequential circuits Design a clocked models sequential circuits State reduction and assignment	Sequential circuits Latches Flip-flops Analysis of clocked models sequential circuits Design a clocked models sequential circuits State reduction and assignment
12	5. Synchronous sequential logic	Sequential circuits Latches Flip-flops Analysis of clocked models sequential circuits Design a clocked models sequential circuits State reduction and assignment	Sequential circuits Latches Flip-flops Analysis of clocked models sequential circuits Design a clocked models sequential circuits State reduction and assignment
13	6. Registers and counters	Registers Shift registers Ripple counters Synchornous counters Other counters	Registers Shift registers Ripple counters Synchornous counters Other counters
14	6. Registers and counters	Registers Shift registers Ripple counters Synchornous counters Other counters	Registers Shift registers Ripple counters Synchornous counters Other counters
15	6. Registers and counters	Registers Shift registers Ripple counters Synchornous counters Other counters	Registers Shift registers Ripple counters Synchornous counters Other counters
16	期末考週	期末考週	期末考週

彈性教學週活動規劃

序 No.	實施期間 Period	實施方式 Content	教學說明 Teaching instructions	彈性教學評量方式 Evaluation	備註 Notes
1	起:2024-01-01 迄:2024-01-13	1.同步遠距教學 Synchronous distance learning	registers and counters	線上作業與線上測驗

教學要點概述：
1.自編教材 Handout by Instructor：
□ 1-1.簡報 Slides
□ 1-2.影音教材 Videos
□ 1-3.教具 Teaching Aids
□ 1-4.教科書 Textbook
□ 1-5.其他 Other
□ 2.自編評量工具/量表 Educational Assessment
□ 3.教科書作者提供 Textbook

成績考核 Performance Evaluation：期末考：30% 期中考：30% 彈性教學：10% 平時考：30%

教學資源(Teaching Resources)：
■ 教材電子檔(Soft Copy of the Handout or the Textbook)
■ 課程網站(Website)
課程網站(Website)：網路大學
扣考規定：https://curri.ttu.edu.tw/p/412-1033-1254.php