I5250 教學大綱表

教學大綱表 (106學年度第1學期)

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課程名稱 Course Title	(中文) 計算機系統結構 (英文) Computer System Architecture			開課單位 Departments	資訊工程研究所
				課程代碼 Course No.	I5250
授課教師 Instructor	柯振揚
學分數 Credit	3.0	必/選修 core required/optional	選修	開課年級 Level	研究所
先修科目或先備能力(Course Pre-requisites)：I3250 Computer Organization
課程概述與目標(Course Overview and Goals)：To provide the student with a solid understanding of the key mechanisms of computer architectures and the types of computer design tradeoffs and decisions involved in computer systems design.
教科書(Textbook)	J.L. Hennessy & D.A. Patterson, Computer Architecture: A Quantitative Approach, 5rd edition, Morgan Kaufmann Publishers, 2012
參考教材(Reference)	D.A. Patterson & J.L. Hennessy , Computer Organization & Design, The hardware / Software Interface, Morgan Kaufmann Publishers.

課程大綱 Syllabus			學生學習目標 Learning Objectives	單元學習活動 Learning Activities	學習成效評量 Evaluation	備註 Notes
序 No.	單元主題 Unit topic	內容綱要 Content summary	學生學習目標 Learning Objectives	單元學習活動 Learning Activities	學習成效評量 Evaluation	備註 Notes
1	Fundamentals of Quantitative Design and Analysis	Classes of Computers Trends in Technology Trends in Power and Energy in Integrated Circuits	Learn the quantitative desgin and analysis of computer architecture
2	Fundamentals of Quantitative Design and Analysis	Trends in Cost Measuring, Reporting, and Summarizing Performance Quantitative Principles of Computer Design	Learn the quantitative desgin and analysis of computer architecture
3	Review of memory hierarchy	Cache Performance Six Basic Cache Optimizations	Learn the design of memory hierarchy
4	Review of memory hierarchy	Virtual Memory Protection and Example of Virtual Memory	Learn the design of memory hierarchy
5	Memory Hierarchy Design	Ten Advanced Optimizations of Cache Performance memory Technology and Optimizations Protection: Virtual memory and Virtual Machines	Learn the design of memory hierarchy
6	Pipelining: Basic and Intermediate Concepts	Major Hurdle of Pipekining -- Pipeline Hazards How is Pipelining Implemented?	Learn the pipeline design of processor
7	Pipelining: Basic and Intermediate Concepts	What makes Pipelining Hard to Implement? Extending the MIPS pipeline to Handle Multicycle Operations	Learn the pipeline design of processor
8	Instruction-Level Parallelism and Its Exploitation	Instruction-Level Parallelism: Concepts and Challenges Basic Compiler Techniques for Exposing ILP	Learn the design of instruction parallelism
9	Midterm examination	Examination	Examination
10	Instruction-Level Parallelism and Its Exploitation	Reducing Branch Costs with Advanced Branch Prediction Overcoming Data Hazards with Dynamic Scheduling Dynamic Scheduling: Examples and the Algorithm	Learn the design of instruction parallelism
11	Instruction-Level Parallelism and Its Exploitation	Hardware-Based Speculation Expoiting ILP Using Multiple Issue and Static Scheduling Expoiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation	Learn the design of instruction parallelism
12	Instruction-Level Parallelism and Its Exploitation	Advanced Techniques for Instruction Delivery and Speculation Studies of Limitations of ILP Cross-Cutting Issues: ILP Approaches and the Memory Syatem Multithreading: Exploiting Thread_Level Parallelism to Improve Uniprocessor Throughput	Learn the design of instruction parallelism
13	Data-Level Parallelism in Vector, SIMD, and GPU Architectures	Vector Architecture SIMD Instruction Set Extensions for Multimedia	Learn the design of data-level parallelism
14	Data-Level Parallelism in Vector, SIMD, and GPU Architectures	Graphic Processing Units Detecting and Enhancing Loop-Level Parallelism	Learn the design of data-level parallelism
15	Data-Level Parallelism in Vector, SIMD, and GPU Architectures	Crosscutting Issues Putting It All Together: Mobile versus Server GPUs and Tesla versus Core i7	Learn the design of data-level parallelism
16	Thread-Level Parallelism	Centralized Shared-Memory Architectures Performance of Symmetric Shared-Memory Multiprocessors Distributed Shared-Memory and Directory-Based Coherence	Learn the design of thread-level parallelism
17	Thread-Level Parallelism	Synchronization: The Basics Models of Memory Consistency: An Introduction	Learn the design of thread-level parallelism
18	Final Examination	Final Examination	Final Examination

教學要點概述：
1.自編教材 Handout by Instructor：
□ 1-1.簡報 Slides
□ 1-2.影音教材 Videos
□ 1-3.教具 Teaching Aids
□ 1-4.教科書 Textbook
□ 1-5.其他 Other
□ 2.自編評量工具/量表 Educational Assessment
□ 3.教科書作者提供 Textbook

成績考核 Performance Evaluation：期末考：35% 期中考：35% 其他評量：1% 平時考：12% 作業：17%

教學資源(Teaching Resources)：
□ 教材電子檔(Soft Copy of the Handout or the Textbook)
□ 課程網站(Website)
扣考規定：https://curri.ttu.edu.tw/p/412-1033-1254.php